The processor in a computer typically accesses a storage apparatus by issuing commands to the storage apparatus. In some configurations, commands are temporarily stored in a queue.
As one example, the technology described below relating to a storage apparatus including a disk memory and a flash memory has been proposed. With this storage apparatus, commands received from a host system are inputted into a primary queue, and commands in the queue that are directed at a flash memory are further stored in a flash queue before being outputted to a flash controller.
As one example of an access control technology for a storage apparatus, the disc control apparatus described below that performs write control according to a plurality of disk drives using a “write-after” arrangement has also been proposed. This disc control apparatus assigns a high priority to a disk drive that is a candidate for a destaging process and is the target of a direct access request from a host computer, and when selecting the disk drive to be subjected to the next destaging process, preferentially selects a disk drive with high priority.
See, for example, the following documents:
Japanese Laid-open Patent Publication No. 2015-130150; and
Japanese Laid-open Patent Publication No. 04-4422.
However, access processes whose execution is requested by a processor using commands may include both high-priority processes and low-priority processes. Here, the higher the priority of an access process, the sooner the access process should be executed. However, with a configuration where commands are temporarily registered in a queue and then issued to a storage apparatus, there is the problem that when a large number of commands for low-priority access processes are present in the queue in front of a command for a high-priority access process, it takes a long time before the command for the high-priority access process is issued.
There are also configurations where a queue is provided at the storage apparatus itself. As one example, commands transmitted from a processor are first stored in a queue at the storage apparatus. A command is fetched from the start of the queue and an access operation in keeping with the fetched command is executed. However with this configuration also, when a command for a high-priority access process is transmitted to the storage apparatus in a state where a large number of commands for low-priority access processes remain in the queue in the storage apparatus, it can take a long time before the high-priority access process is executed.